* Spice macromodel for ZXLD1350 inductive converter * * Release V2 .subckt ZXLD1350 18 20 13 10 26 *Connections Vin Isense Adj Lx Gnd * Vref Generator * E2 19 26 18 26 1 D7 26 14 Dzener R3 14 19 200k R4 14 13 200k * ADJ input filter * * Faster (but unrealistic) startup can be * achieved by changing initial conditions * on C1 to C3 to match the settled value. * eg 1.25V if ADJ is floating in the application * or equal to the external DC voltage applied to ADJ * or equal to the average value of the PWM signal * applied to ADJ C1 15 26 5p IC=0 C2 16 26 5p IC=0 C3 17 26 5p IC=0 R5 13 15 7.7meg R6 15 16 7.7meg R7 16 17 7.7meg E7 12 26 17 26 1 * ADJ lockout with hysteresis * R8 12 adj_lockout 1000 I1 12 adj_lockout DC 50uA C7 adj_lockout 12 1p IC=0 X_S4 adj_lockout 26 adj_lockout 12 ZXLD1350_S4 X_S5 adj_lockout 26 23 26 ZXLD1350_S5 * UV lockout * X_S6 18 26 23 26 ZXLD1350_S6 * Main Function * G2 26 8 18 20 1m C4 26 20 20p R9 26 9 3.832k R10 9 8 10.859k X_S7 23 26 9 26 ZXLD1350_S7 G3 21 26 8 12 1000m R11 26 21 1meg V3 24 26 700mV D8 24 21 Dclamp V4 22 26 6V D9 21 22 Dclamp * Comp Delay (Asymmetric) * E4 25 26 21 26 1 C6 26 23 25p R13 23 25 2k * Output NMOS * X_S8 23 26 11 26 ZXLD1350_S8 R12 11 10 0.4 C5 26 10 100p * Supply Current * X_S3 adj_lockout 26 4 7 ZXLD1350_S3 R1 26 7 1.58k R2 26 4 67k X_S2 18 26 6 4 ZXLD1350_S2 V1 5 26 1V X_F1 6 5 18 26 ZXLD1350_F1 * Timestep Control * * Only purpose is to force timestep without using a control card * V99 99 26 DC 0 AC 0 PULSE 0 0 0 100n 100n 500n 1u R99 99 26 100 .model Dzener D Is=1e-8 N=10 bv=1.245 ibv=1e-12 Cjo=.1e-12 Rs=.1 TBV1=4e-5 nbv=.01 .model Dclamp D Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m Cjo=4p M=.3333 Vj=.5 .ends ZXLD1350 .subckt ZXLD1350_F1 1 2 3 4 F_F1 3 4 VF_F1 1 VF_F1 1 2 0V .ends ZXLD1350_F1 .subckt ZXLD1350_S3 1 2 3 4 S_S3 3 4 1 2 S3 RS_S3 1 2 1G .MODEL S3 VSWITCH Roff=1e6 Ron=1.0 Voff=198mV Von=200mV .ends ZXLD1350_S3 .subckt ZXLD1350_S2 1 2 3 4 S_S2 3 4 1 2 S2 RS_S2 1 2 1G .MODEL S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1.248V Von=1.25V .ends ZXLD1350_S2 .subckt ZXLD1350_S6 1 2 3 4 S_S6 3 4 1 2 S6 RS_S6 1 2 1G .MODEL S6 VSWITCH Roff=10e6 Ron=1.0 Voff=6.505V Von=6.495V .ends ZXLD1350_S6 .subckt ZXLD1350_S7 1 2 3 4 S_S7 3 4 1 2 S7 RS_S7 1 2 1G .MODEL S7 VSWITCH Roff=10e6 Ron=1.0 Voff=2750mV Von=2755mV .ends ZXLD1350_S7 .subckt ZXLD1350_S8 1 2 3 4 S_S8 3 4 1 2 S8 RS_S8 1 2 1G .MODEL S8 VSWITCH Roff=10e6 Ron=1.0 Voff=2750mV Von=2755mV .ends ZXLD1350_S8 .subckt ZXLD1350_S4 1 2 3 4 S_S4 3 4 1 2 S4 RS_S4 1 2 1G .MODEL S4 VSWITCH Roff=10e6 Ron=1 Voff=255mV Von=245mV .ends ZXLD1350_S4 .subckt ZXLD1350_S5 1 2 3 4 S_S5 3 4 1 2 S5 RS_S5 1 2 1G .MODEL S5 VSWITCH Roff=10e6 Ron=1.0 Voff=251mV Von=249mV .ends ZXLD1350_S5